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<title>VCVTSD2USI—Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer </title></head>
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<h1>VCVTSD2USI—Convert Scalar Double-Precision Floating-Point Value to Unsigned Doubleword Integer</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op /En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>
<p>EVEX.LIG.F2.0F.W0 79 /r</p>
<p>VCVTSD2USI r32, xmm1/m64{er}</p></td>
<td>T1F</td>
<td>V/V</td>
<td>AVX512F</td>
<td>Convert one double-precision floating-point value from xmm1/m64 to one unsigned doubleword integer r32.</td></tr>
<tr>
<td>
<p>EVEX.LIG.F2.0F.W1 79 /r</p>
<p>VCVTSD2USI r64, xmm1/m64{er}</p></td>
<td>T1F</td>
<td>V/N.E.<sup>1</sup></td>
<td>AVX512F</td>
<td>Convert one double-precision floating-point value from xmm1/m64 to one unsigned quadword integer zero-extended into r64.</td></tr></table>
<p><strong>NOTES: 1. EVEX.W1 in non-64 bit is ignored; the instructions behaves as if the W0 version is used.</strong></p>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td>
<td>Operand 4</td></tr>
<tr>
<td>T1F</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td>
<td>NA</td></tr></table>
<p><strong>Description</strong></p>
<p>Converts a double-precision floating-point value in the source operand (the second operand) to an unsigned doubleword integer in the destination operand (the first operand). The source operand can be an XMM register or a 64-bit memory location. The destination operand is a general-purpose register. When the source operand is an XMM register, the double-precision floating-point value is contained in the low quadword of the register.</p>
<p>When a conversion is inexact, the value returned is rounded according to the rounding control bits in the MXCSR register or the embedded rounding control bits. If a converted result cannot be represented in the destination format, the floating-point invalid exception is raised, and if this exception is masked, the integer value 2<sup>w</sup> – 1 is returned, where w represents the number of bits in the destination format.</p>
<p><strong>Operation</strong></p>
<p><strong>VCVTSD2USI (EVEX encoded version)</strong></p>
<p>IF (SRC *is register*) AND (EVEX.b = 1)</p>
<p>THEN</p>
<p>SET_RM(EVEX.RC);</p>
<p>ELSE</p>
<p>SET_RM(MXCSR.RM);</p>
<p>FI;</p>
<p>IF 64-Bit Mode and OperandSize = 64</p>
<p>THEN</p>
<p>DEST[63:0] (cid:197) Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]);</p>
<p>ELSE</p>
<p>DEST[31:0] (cid:197) Convert_Double_Precision_Floating_Point_To_UInteger(SRC[63:0]);</p>
<p>FI</p>
<p><strong>Intel C/C++ Compiler Intrinsic Equivalent</strong></p>
<p>VCVTSD2USI unsigned int _mm_cvtsd_u32(__m128d);</p>
<p>VCVTSD2USI unsigned int _mm_cvt_roundsd_u32(__m128d, int r);</p>
<p>VCVTSD2USI unsigned __int64 _mm_cvtsd_u64(__m128d);</p>
<p>VCVTSD2USI unsigned __int64 _mm_cvt_roundsd_u64(__m128d, int r);</p>
<p><strong>SIMD Floating-Point Exceptions</strong></p>
<p>Invalid, Precision</p>
<p><strong>Other Exceptions</strong></p>
<p>EVEX-encoded instructions, see Exceptions Type E3NF.</p></body></html>